Processing systems may include a backing storage location such as a memory subsystem comprising a main memory. For main memory implementations with large storage capacity, e.g., utilizing double-data rate (DDR) implementations of dynamic random access memory (DRAM) technology, the memory subsystem may be implemented off-chip, e.g., integrated on a memory chip which is different from a processor chip or system on chip (SoC) on which one or more processors which access the memory subsystem are integrated. Accordingly, accessing the main memory involves transporting data between the memory subsystem and the SoC, which has associated costs in terms of power consumption.
Power consumption in memory systems is a well-recognized challenge. Several techniques are known in the art for reducing power consumption in memory, such as voltage scaling. For example, the trend in voltage scaling is seen by considering the supply voltages specified for several generations or versions of low power DDR (LPDDR). The supply voltage VDD is 1.8V for LPDDR1; 1.2V for LPDDR2 and LPDDR3; 1.1V for LPDDR4. However, for future generations (e.g., LPDDR5, and beyond) the scope for further voltage scaling is limited, because if supply voltage continues to reduce, performance degradations may be observed due to limitations imposed by refresh operations and performance of memory peripheral input/output (IO) circuitry. Thus, any power efficiency gains which may be achieved by further voltage scaling may be offset by performance and quality degradations.
Accordingly, there is a need in the art for improving power efficiency of existing and future generations of memory subsystems, while avoiding drawbacks of conventional approaches such as voltage scaling.